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description the CXA2079Q is a 6-input, 2-output audio/video switch featuring i 2 c bus compatibility for tvs. this ic has input pins that are compatible with s2 protocol. features 4 inputs that are compatible with s2 protocol serial control with i 2 c bus 6 inputs, 2 outputs the desired inputs can be selected independently for each of the 2 outputs wide band video amplifier (20mhz, ?db) y/c mix circuit slave address can be changed (90h/92h) audio muting from external pin high impedance maintained by i 2 c bus lines (sda, scl) even when power is off wide audio dynamic range (3vrms typ.) applications audio/video switch featuring i 2 c bus compatibility for tvs structure bipolar silicon monolithic ic absolute maximum ratings supply voltage v cc 12 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d 1300 mw operating conditions supply voltage 9 0.5 v ?1 CXA2079Q e97430a7y s2-compatible 6-input 2-output audio/video switch sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 64 pin qfp (plastic)
? 2 CXA2079Q block diagram 2 9 3 0 3 1 4 6 4 7 v o u t 1 y o u t 1 l v 5 v 5 r v 5 l t v t v r t v n c n c n c c 4 r v 4 y 4 l v 4 v 4 v 3 v 2 v 1 y 3 y 2 y 1 c 3 c 2 c 1 l v 3 l v 2 l v 1 r v 3 r v 2 r v 1 n c n c y i n 1 l o u t 1 r o u t 1 t r a p 1 v g n d c o u t 1 c i n 1 v o u t 2 y i n 2 y o u t 2 c o u t 2 c i n 2 a g n d 2 b i a s v c c a g n d l o u t 2 r o u t 2 6 d b 6 d b 6 d b 6 d b 6 d b 6 d b b i a s 6 d b 0 d b 6 d b 0 d b 6 d b 6 d b 4 9 5 3 5 6 4 0 3 9 3 8 3 7 3 5 4 1 4 2 4 3 4 4 4 5 a d r s - 4 s 2 - 4 s - 3 s 2 - 3 s d a s c l d c o u t s - 2 s - 1 s 2 - 2 s 2 - 1 m u t e l o g i c 6 7 1 3 1 4 2 0 2 1 2 7 2 8 3 6 3 4 3 2 3 3 4 8 5 0 5 1 5 2 5 4 5 5 5 7 5 8 4 1 1 1 8 2 5 6 4 6 1 8 1 5 2 2 6 0 6 3 1 3 5 1 0 1 2 1 7 1 9 2 4 2 6 2 9 1 6 2 3 5 9 6 2 audio system is attenuated by 6db for 6k resistor input, and a total gain is 0db (lout1 and rout1 can be changed to ?db).
? 3 CXA2079Q pin configuration 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 1 l o u t 1 v o u t 1 r o u t 1 t r a p 1 y o u t 1 v g n d c o u t 1 l v 5 v 5 r v 5 l t v t v r t v a d r n c n c n c s - 4 s 2 - 4 c 4 r v 4 y 4 l v 4 v 4 s - 3 s 2 - 3 c i n 1 b i a s y i n 1 m u t e n c n c y i n 2 a g n d 2 c i n 2 v c c v o u t 2 r o u t 2 y o u t 2 l o u t 2 c o u t 2 d c o u t a g n d s d a s c l v 1 l v 1 y 1 r v 1 c 1 s 2 - 1 s - 1 v 2 l v 2 y 2 r v 2 c 2 s 2 - 2 s - 2 v 3 l v 3 y 3 r v 3 c 3
? 4 CXA2079Q pin description pin no. 63 1 8 15 22 60 tv v1 v2 v3 v4 v5 4.0v video signal inputs. input composite video signals. symbol pin voltage equivalent circuit description 1 5 0 v c c 3 a 8 1 5 2 2 6 0 6 3 1 3 10 17 24 49 45 y1 y2 y3 y4 yin1 yin2 4.0v y/c separation signal inputs. input luminance signals. the yin1 pin inputs the signal obtained by y/c separating the vout1 pin output. the yin2 pin inputs the signal obtained by y/c separating the vout2 pin output. 3 1 0 1 7 2 4 4 5 4 9 1 5 0 v c c 3 a 5 12 19 26 51 43 c1 c2 c3 c4 cin1 cin2 4.5v y/c separation signal inputs. input chrominance signals. the cin1 pin inputs the signal obtained by y/c separating the vout1 pin output. the cin2 pin inputs the signal obtained by y/c separating the vout2 pin output. 1 5 0 v c c 2 7 k 2 0 k 5 1 2 1 9 2 6 4 3 5 1 62 2 9 16 23 59 64 4 11 18 25 61 ltv lv1 lv2 lv3 lv4 lv5 rtv rv1 rv2 rv3 rv4 rv5 4.5v audio signal inputs. v c c 1 5 k 3 3 k 2 7 k 2 4 9 1 1 1 6 1 8 2 3 2 5 5 9 6 4 6 1 6 2 53 41 vout1 vout2 3.9v video signal outputs. output composite video signals. v c c 2 7 k v c c 2 3 . 5 k 3 0 k 2 5 0 4 1 5 3
? 5 CXA2079Q 58 37 cout1 cout2 4.5v video signal outputs. output chrominance signals. v c c v c c v c c v c c 3 7 5 8 56 39 yout1 yout2 3.3v video signal outputs. output luminance signals. v c c v c c v c c v c c 3 9 5 6 52 38 54 40 lout1 lout2 rout1 rout2 4.5v audio signal outputs. zo = 50 (within dc 2ma) v c c v c c v c c 1 4 7 1 0 0 k 6 1 3 2 0 2 7 6 13 20 27 s2-1 s2-2 s2-3 s2-4 detects the s2-compatible dc superimposed onto the c signal. 4:3 video signal at 1.3v or less 4:3 letter-box signal at 1.3v or more to 2.5v or less 16:9 picture squeezed signal at 2.5v or more these pins are pulled down to gnd by a 100k resistor, so the 4:3 video signals are selected when open. v c c v c c 2 0 k 5 6 2 0 k 4 0 3 8 5 2 5 4 7 14 21 28 s-1 s-2 s-3 s-4 composite video/s selector. the detection results are written to the status register. s signal at 3.5v or less composite video signal at 3.5v or more these pins are pulled up to 5v by a 100k resistor, so the composite video signals are selected when open. v c c v c c v c c 5 0 k 1 0 k 1 0 0 k 5 0 k 5 v 7 1 4 2 1 2 8 32 adr selects the slave address for the i 2 c bus. 90h at 1.5v or less 92h at 2.5v or more 90h when open v c c 1 4 7 2 8 k 7 2 k 3 2 pin no. symbol pin voltage equivalent circuit description
? 6 CXA2079Q 34 sda i 2 c bus signal input v il max = 1.5v v ih min = 3.0v v ol max = 0.4v v c c 4 k 3 4 33 scl i 2 c bus signal input v il max = 1.5v v ih min = 3.0v 3 3 v c c 4 k 1 0 k 36 dc out outputs the s2-compatible dc superimposed onto the cout2 output. the dc is superimposed by connecting this pin to the cout2 output via a capacitor. control is performed by the i 2 c bus. when 0v is output, q1 is on and the impedance is 5k . s2 protocol output dc impedance of 10 3k is realized by attaching external resistance of 4.7k . dc out (bus) output dc 0 4.5v 1 0v 2 1.9v 3 4.5v v c c 1 0 0 1 k 5 5 55 trap1 3.8v connects trap circuit for subcarrier. 3 6 v c c 4 k 2 8 k 1 k q 1 48 mute audio signal output mute. mute off at 1.5v or less mute on at 2.5v or more mute off when open v c c 1 4 7 2 8 k 7 2 k 4 8 50 bias 4.5v internal reference bias (vcc/2). connects to gnd via a capacitor. v c c v c c 1 4 7 2 0 k v c c 2 0 k 5 0 pin no. symbol pin voltage equivalent circuit description
? 7 CXA2079Q electrical characteristics (ta = 25 c, v cc = 9v) item current consumption i cc no signal, no load 30 45 62 ma symbol conditions min. typ. max. unit video system (measurement circuit; fig. 1) gain frequency response characteristics frequency response characteristics (y/c mix) input dynamic range cross talk gvv fbwv1 fbwv2 ddv vctv f = 100khz, 0.3vp-p input f = 100khz, input frequency where output amplitude is ?db with 0.3vp-p output serving as 0db f = 100khz, maximum with distortion < 1.0% f = 4.43mhz, 1vp-p input 5.9 15 10 1.4 6.4 20 15 6.9 ?0 db mhz mhz vp-p db audio system (measurement circuits; fig. 2 to fig. 5) gain frequency response characteristics total harmonic distortion input dynamic range cross talk ripple rejection ratio output dc offset residual noise s/n ratio gv a fbw a thd dd a vct a vct a voff vn a s/n f = 1khz, 1vp-p input, 5.7k resistor inserted to input f = 1khz, input frequency where output amplitude is ?db with 1vp-p output serving as 0db f=1khz, 2.2vp-p input, where 400hz hpf + 80khz lpf are inserted f=1khz, maximum with distortion < 0.3% f=1khz, 1vp-p input f=100hz, 0.3vp-p applied to vcc offset voltage between input and output when 400hz hpf+ 30khz lpf are inserted f=1khz, 1vrms input when 400hz hpf + 30khz lpf are inserted ? 50 2.8 ?0 0 0 0.03 3.0 ?0 ?5 20 ?00 1 0.05 ?0 ?0 30 30 ?0 db khz % vrms db db mv vrms db
? 8 CXA2079Q high level input voltage low level input voltage low level output voltage high level input current low level input current maximum clock frequency minimum waiting time for data change minimum waiting time for data transfer start low level clock pulse width high level clock pulse width minimum waiting time for start preparation minimum data hold time minimum data preparation time rise time fall time minimum waiting time for stop preparation v ih v il v ol i ih i il f scl t buf t hd;sta t low t high t su;sta t hd;dat t su;dat t r t f t su;sto with sda 3ma current supplied v ih = 4.5v v il = 0.4v 3.0 0 0 0 0 0 4.7 4.0 4.7 4.0 4.7 0 250 4.7 5.0 1.5 0.4 10 10 100 1 300 v v v a a khz s s s s s ns ns s ns s logic system item symbol conditions min. typ. max. unit
? 9 CXA2079Q 0 . 4 7 7 5 1 0 1 0 k 1 0 1 0 1 0 1 0 k 1 0 k 1 0 k 0 . 1 0 . 4 7 7 5 1 0 . 4 7 1 7 5 7 5 0 . 1 0 . 4 7 6 0 0 7 5 1 0 . 4 7 6 0 0 1 7 5 0 . 1 0 . 4 7 7 5 1 0 . 4 7 1 7 5 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 1 l o u t 1 v o u t 1 r o u t 1 t r a p 1 y o u t 1 v g n d c o u t 1 l v 5 v 5 r v 5 l t v t v r t v a d r n c n c n c s - 4 s 2 - 4 c 4 r v 4 y 4 l v 4 v 4 s - 3 s 2 - 3 c i n 1 b i a s y i n 1 m u t e n c n c y i n 2 a g n d 2 c i n 2 v c c v o u t 2 r o u t 2 y o u t 2 l o u t 2 c o u t 2 d c o u t a g n d s d a s c l v 1 l v 1 y 1 r v 1 c 1 s 2 - 1 s - 1 v 2 l v 2 y 2 r v 2 c 2 s 2 - 2 s - 2 v 3 l v 3 y 3 r v 3 c 3 0 . 4 7 1 0 . 4 7 1 0 . 1 2 2 1 k 1 0 1 0 . 4 7 1 1 0 . 4 7 1 7 5 6 0 0 7 5 6 0 0 7 5 7 5 6 0 0 6 0 0 7 5 6 0 0 6 0 0 7 5 1 0 6 0 0 6 0 0 7 5 6 0 0 6 0 0 1 0 k i n p u t s i g n a l m e a s u r e m e n t p o i n t - c o m 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 0 . 1 7 5 0 . 4 7 7 5 0 . 1 7 5 fig. 1. video system (gain, frequency response characteristics, input dynamic range, cross talk) measurement circuit signal is input from one of the following pins: 1, 3, 5, 8, 10, 12, 15, 17, 19, 22, 24, 26, 60 and 63. output signal is measured from one of the following pins: 37, 39, 41, 53, 56 and 58.
? 10 CXA2079Q 1 6 0 0 5 . 7 k 1 6 0 0 5 . 7 k 1 6 0 0 5 . 7 k 0 . 1 0 . 4 7 6 0 0 7 5 1 0 . 4 7 6 0 0 1 7 5 7 5 5 . 7 k 5 . 7 k 0 . 1 0 . 4 7 6 0 0 7 5 1 0 . 4 7 6 0 0 1 7 5 7 5 5 . 7 k 5 . 7 k 0 . 4 7 7 5 1 0 1 0 k 1 0 1 0 1 0 1 0 k 1 0 k 1 0 k 0 . 1 0 . 4 7 6 0 0 7 5 1 0 . 4 7 6 0 0 1 7 5 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 1 l o u t 1 v o u t 1 r o u t 1 t r a p 1 y o u t 1 v g n d c o u t 1 l v 5 v 5 r v 5 l t v t v r t v a d r n c n c n c s - 4 s 2 - 4 c 4 r v 4 y 4 l v 4 v 4 s - 3 s 2 - 3 c i n 1 b i a s y i n 1 m u t e n c n c y i n 2 a g n d 2 c i n 2 v c c v o u t 2 r o u t 2 y o u t 2 l o u t 2 c o u t 2 d c o u t a g n d s d a s c l v 1 l v 1 y 1 r v 1 c 1 s 2 - 1 s - 1 v 2 l v 2 y 2 r v 2 c 2 s 2 - 2 s - 2 v 3 l v 3 y 3 r v 3 c 3 0 . 4 7 1 0 . 4 7 1 0 . 1 2 2 1 k 1 0 0 . 4 7 0 . 4 7 1 7 5 6 0 0 7 5 6 0 0 7 5 7 5 7 5 1 0 6 0 0 7 5 1 0 k i n p u t s i g n a l m e a s u r e m e n t p o i n t - c o m 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 0 . 1 7 5 0 . 4 7 7 5 0 . 1 7 5 5 . 7 k 5 . 7 k 5 . 7 k 5 . 7 k 5 . 7 k fig. 2. audio system (gain, frequency response characteristics, total harmonic distortion, input dynamic range, cross talk) mea surement circuit signal is input from one of the following pins: 2, 4, 9, 11, 16, 18, 23, 25, 59, 61, 62 and 64. output signal is measured from one of the following pins: 38, 40, 52 and 54.
? 11 CXA2079Q 1 1 6 0 0 6 0 0 0 . 1 0 . 4 7 6 0 0 7 5 0 . 4 7 7 5 7 5 1 6 0 0 1 0 . 1 0 . 4 7 6 0 0 7 5 0 . 4 7 7 5 7 5 1 6 0 0 1 1 6 0 0 1 6 0 0 1 6 0 0 0 . 1 0 . 4 7 6 0 0 7 5 0 . 4 7 7 5 7 5 0 . 4 7 7 5 1 0 1 0 k 1 0 1 0 1 0 1 0 k 1 0 k 1 0 k 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 1 l o u t 1 v o u t 1 r o u t 1 t r a p 1 y o u t 1 v g n d c o u t 1 l v 5 v 5 r v 5 l t v t v r t v a d r n c n c n c s - 4 s 2 - 4 c 4 r v 4 y 4 l v 4 v 4 s - 3 s 2 - 3 c i n 1 b i a s y i n 1 m u t e n c n c y i n 2 a g n d 2 c i n 2 v c c v o u t 2 r o u t 2 y o u t 2 l o u t 2 c o u t 2 d c o u t a g n d s d a s c l v 1 l v 1 y 1 r v 1 c 1 s 2 - 1 s - 1 v 2 l v 2 y 2 r v 2 c 2 s 2 - 2 s - 2 v 3 l v 3 y 3 r v 3 c 3 0 . 4 7 0 . 4 7 0 . 1 1 k 1 0 0 . 4 7 0 . 4 7 1 7 5 7 5 7 5 7 5 1 0 6 0 0 7 5 1 0 k m e a s u r e m e n t p o i n t - c o m 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 0 . 1 7 5 0 . 4 7 7 5 0 . 1 7 5 1 6 0 0 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 1 0 0 h z , 0 . 3 v p - p fig. 3. audio system (ripple rejection ratio) measurement circuit a f=100hz, 0.3vp-p signal is applied to vcc and the output signals from pins 38, 40, 52 and 54 are measured.
? 12 CXA2079Q 1 6 0 0 5 . 7 k 1 6 0 0 5 . 7 k 1 6 0 0 5 . 7 k 0 . 1 0 . 4 7 6 0 0 7 5 1 0 . 4 7 6 0 0 1 7 5 7 5 5 . 7 k 5 . 7 k 0 . 1 0 . 4 7 6 0 0 7 5 1 0 . 4 7 6 0 0 1 7 5 7 5 5 . 7 k 5 . 7 k 0 . 4 7 7 5 1 0 1 0 k 1 0 1 0 1 0 1 0 k 1 0 k 1 0 k 0 . 1 0 . 4 7 6 0 0 7 5 1 0 . 4 7 6 0 0 1 7 5 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 1 l o u t 1 v o u t 1 r o u t 1 t r a p 1 y o u t 1 v g n d c o u t 1 l v 5 v 5 r v 5 l t v t v r t v a d r n c n c n c s - 4 s 2 - 4 c 4 r v 4 y 4 l v 4 v 4 s - 3 s 2 - 3 c i n 1 b i a s y i n 1 m u t e n c n c y i n 2 a g n d 2 c i n 2 v c c v o u t 2 r o u t 2 y o u t 2 l o u t 2 c o u t 2 d c o u t a g n d s d a s c l v 1 l v 1 y 1 r v 1 c 1 s 2 - 1 s - 1 v 2 l v 2 y 2 r v 2 c 2 s 2 - 2 s - 2 v 3 l v 3 y 3 r v 3 c 3 0 . 4 7 1 0 . 4 7 1 0 . 1 2 2 1 k 1 0 0 . 4 7 0 . 4 7 1 7 5 6 0 0 7 5 6 0 0 7 5 7 5 7 5 1 0 6 0 0 7 5 1 0 k m e a s u r e m e n t p o i n t m e a s u r e m e n t p o i n t - c o m 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 0 . 1 7 5 0 . 4 7 7 5 0 . 1 7 5 5 . 7 k 5 . 7 k 5 . 7 k 5 . 7 k 5 . 7 k fig. 4. audio system (output dc offset voltage) measurement circuit
? 13 CXA2079Q 1 1 6 0 0 6 0 0 0 . 1 0 . 4 7 6 0 0 7 5 0 . 4 7 7 5 7 5 1 6 0 0 1 0 . 1 0 . 4 7 6 0 0 7 5 0 . 4 7 7 5 7 5 1 6 0 0 1 1 6 0 0 1 6 0 0 1 6 0 0 0 . 1 0 . 4 7 6 0 0 7 5 0 . 4 7 7 5 7 5 0 . 4 7 7 5 1 0 1 0 k 1 0 1 0 1 0 1 0 k 1 0 k 1 0 k 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 1 l o u t 1 v o u t 1 r o u t 1 t r a p 1 y o u t 1 v g n d c o u t 1 l v 5 v 5 r v 5 l t v t v r t v a d r n c n c n c s - 4 s 2 - 4 c 4 r v 4 y 4 l v 4 v 4 s - 3 s 2 - 3 c i n 1 b i a s y i n 1 m u t e n c n c y i n 2 a g n d 2 c i n 2 v c c v o u t 2 r o u t 2 y o u t 2 l o u t 2 c o u t 2 d c o u t a g n d s d a s c l v 1 l v 1 y 1 r v 1 c 1 s 2 - 1 s - 1 v 2 l v 2 y 2 r v 2 c 2 s 2 - 2 s - 2 v 3 l v 3 y 3 r v 3 c 3 0 . 4 7 0 . 4 7 0 . 1 1 k 1 0 0 . 4 7 0 . 4 7 1 7 5 7 5 7 5 7 5 1 0 6 0 0 7 5 1 0 k m e a s u r e m e n t p o i n t - c o m 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 1 0 1 0 k 0 . 1 7 5 0 . 4 7 7 5 0 . 1 7 5 1 6 0 0 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 4 . 5 v 2 2 4 0 d b fig. 5. audio system (residual noise) measurement circuit
? 14 CXA2079Q i 2 c bus control signal t s u ; s t o 3 4 3 3 t s u ; s t a s p t h i g h t f t s u ; d a t t l o w t r t h d ; d a t s p t h d ; s t a t b u f s c l s d a fig. 6. i 2 c bus control signal timing chart description of operation the CXA2079Q is a tv i 2 c bus-compatible av switch ic. the video system and the stereo audio system both have 6 inputs and 2 outputs each. 4 of the 6 video system inputs support s2 and s protocols. the desired inputs can be independently assigned to each output (in the audio system, the left and right channels are processed as one unit) by i 2 c bus control. however, the same input is assigned to both the video and audio system output 2. i 2 c bus registers 1) i 2 c bus the i 2 c bus (inter-ic bus) is an inter-ic bus system developed by philips. two lines (sda ?serial data, scl serial clock) provide control over start, stop, data transfer, synchronization, and collision avoidance. the ic outputs are either open collector or open drain, forming a bus line in the wired or format. s c l s d a s p m s b l s b a m s b l s b a 9 2 1 9 8 7 6 5 4 3 2 1 s : s t a r t c o n d i t i o n ; s d a i s s e t " l o w " w h e n s c l i s " h i g h " p : s t o p c o n d i t i o n ; s d a i s s e t " h i g h " w h e n s c l i s " h i g h " a : a c k n o w l e d g e ; s i g n a l s e n t f r o m t h e s l a v e data is transmitted by msb-first. one data unit consists of 8 bits, to which the acknowledge signal, which indicates that the data has been accepted by the slave, is attached at the end. normally, the slave * 1 ic receives data at the rising edge of scl and the master * 2 ic changes data at the falling edge of scl. * 1 slave: an ic that is placed under the control of the master. in a normal system, all devices excluding the central microcomputer are slaves. * 2 master: a central microcomputer or other controlling ic.
? 15 CXA2079Q 2) control registers the CXA2079Q control is exercised by writing 2-byte data into the two 8-bit control registers which control the output selector circuits for the 2 outputs. s slave address a data1 a data2 a p s: start condition a: acknowledge p: stop condition control register structure (data1 and data2) all registers are set to "0" during ic power on. " * " indicates undefined. slave add. data1 data2 1 a-gain * 0 s/comp1 s/comp2 0 v-in1 av-in2 1 0 0 dc out adr a-in1 r/w b7 b6 b5 b4 b3 b2 b1 b0 * r/w (1): read/write mode 0: control data write 1: status register read adr (1): this bit sets the slave address set by the address pin. 0: 90h 1: 92h a-gain (1): lout1/rout1 output gain selector 0: 0db output 1: ?db output s/comp1 and s/comp2 (1 each): s terminal input/composite signal input selectors by setting these bits to "0", when composite signal input is selected, yout/cout output the inputs from yin/cin during video 1/2 output. 0: composite signal inputs (tv, v1 to v5 inputs) 1: s terminal inputs (y1/c1 to y4/c4 inputs) v-in1 (3 each): this bit selects the input signals output to each video output. 0: mute 1: selects the tv input 2: selects the v1 and y1/c1 inputs 3: selects the v2 and y2/c2 inputs 4: selects the v3 and y3/c3 inputs 5: selects the v4 and y4/c4 inputs 6: selects the v5 input 7: mute
? 16 CXA2079Q a-in1 (3 each): this bit selects the input signals output to each audio output. 0: mute 1: selects the ltv/rtv inputs 2: selects the lv1/rv1 inputs 3: selects the lv2/rv2 inputs 4: selects the lv3/rv3 inputs 5: selects the lv4/rv4 inputs 6: selects the lv5/rv5 inputs 7: mute av-in2 (3): this bit selects the input signals output to output 2 (vout2, yout2/cout2, lout2/rout2). note) both the video output and the audio output are selected at the same time only for av-in2. 0: mute 1: selects the tv and ltv/rtv inputs 2: selects the v1, y1/c1 and lv1/rv1 inputs 3: selects the v2, y2/c2 and lv2/rv2 inputs 4: selects the v3, y3/c3 and lv3/rv3 inputs 5: selects the v4, y4/c4 and lv4/rv4 inputs 6: selects the v5 and lv5/rv5 inputs 7: mute dc out (2): this bit sets the dc voltage output from pin 36 (dc out). 0: 4.5v 1: 0v 2: 1.9v 3: 4.5v 3) status registers when reading two bytes s slave address a data1 a data2 na p s: start condition a: acknowledge na: no acknowledge p: stop condition when reading one byte s slave address a data1 na p when communication is to be terminated in the status register reading mode, the no-acknowledge signal is needed to assure that the master does not issue the acknowledge signal to the slave. it is possible to read only data1 of the status register by sending the no-acknowledge signal after data1.
? 17 CXA2079Q s-c1, s-c2, s-c3, s-c4 (2 each): s2-1, s2-2, s2-3 and s2-4 pin status 0: 4:3 video signal 1: 4:3 letter-box signal 2: 16:9 video squeezed signal 3: no signal s-c1 to s-c4 are actually determined by comparing the s2-1 to s2-4 pin dc voltages with two threshold. however, when the s-1 to s-4 pins are open, the outputs are fixed to "3". s2-1 to s2-4 pin dc voltage s-c1 to s-c4 1.3v or less 1.3v or more to 2.5v or less 2.5v or more s-1 to s-4 open 0 1 2 3 status register structure (data1 and data2) slave add. data1 data2 1 s1sel s1sel 0 s2sel s2sel s3sel s3sel s4sel s4sel 0 1 0 0 s-c1 s-c3 adr s-c2 s-c4 1 b7 b6 b5 b4 b3 b2 b1 b0 s1sel to s4sel (1 each): s-1 to s-4 pin status 0: s-1 to s-4 pins are not grounded. 1: s-1 to s-4 pins are grounded. s1sel to s4sel are actually determined by comparing the s-1 to s-4 pin dc voltages with 3.5v. s-1 to s-4 pin dc voltage s1sel to s4sel 3.5v or more 3.5v or less 0 1 4) power-on reset the CXA2079Q has an internal power-on reset function that sets each control register to "0" during ic power on. the power-on reset v th has hysteresis. p o w e r - o n r e s e t r e l e a s e d p o w e r - o n r e s e t 4 . 5 v 5 . 6 v v c c
? 18 CXA2079Q c o m b f i l t e r 0 . 1 0 . 4 7 4 7 0 k 7 5 1 0 . 4 7 4 7 0 k 1 7 5 1 7 5 0 . 1 0 . 4 7 4 7 0 k 7 5 1 0 . 4 7 4 7 0 k 1 7 5 1 7 5 0 . 1 0 . 4 7 4 7 0 k 7 5 1 0 . 4 7 4 7 0 k 1 7 5 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 1 l o u t 1 v o u t 1 r o u t 1 t r a p 1 y o u t 1 v g n d c o u t 1 l v 5 v 5 r v 5 l t v t v r t v a d r n c n c n c s - 4 s 2 - 4 c 4 r v 4 y 4 l v 4 v 4 s - 3 s 2 - 3 c i n 1 b i a s y i n 1 m u t e n c n c y i n 2 a g n d 2 c i n 2 v c c v o u t 2 r o u t 2 y o u t 2 l o u t 2 c o u t 2 d c o u t a g n d s d a s c l v 1 l v 1 y 1 r v 1 c 1 s 2 - 1 s - 1 v 2 l v 2 y 2 r v 2 c 2 s 2 - 2 s - 2 v 3 l v 3 y 3 r v 3 c 3 1 7 5 0 . 4 7 1 0 . 4 7 1 0 . 1 1 6 2 0 1 8 0 0 . 1 4 . 7 k 7 5 2 2 0 2 2 0 2 2 c o m b f i l t e r 1 k 0 . 4 7 1 0 0 . 1 1 0 p 1 0 . 4 7 1 1 0 . 4 7 1 v i d e o 1 i n p u t v i d e o 2 i n p u t v i d e o 3 i n p u t v i d e o 4 i n p u t v i d e o 2 o u t p u t v i d e o 1 o u t p u t v i d e o 5 i n p u t t v i n p u t - c o m 7 5 0 . 4 7 0 . 1 application circuit depending on the output bias of the comb filters, pay attention to the polarities of the capacitors since the bias at pins 43, 45, 49 and 51 is approximately 3.1v and 4.5v, respectively. connect pin 32 to vcc when setting the slave address of the ic to 92h. the audio output can be muted by setting pin 48 to 3.5v or more. the trap (pin 55) are of 3.58mhz subcarrier. pay attention to the polarities of the capacitors since each output of video system and audio system has optional bias, respectively. application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 19 CXA2079Q example of representative characteristics v i d e o s y s t e m f r e q u e n c y r e s p o n s e c h a r a c t e r i s t i c s 1 0 0 k 2 f r e q u e n c y [ h z ] 1 m 1 0 m 1 0 0 m 0 2 4 6 8 v i d e o s y s t e m i n p u t / o u t p u t g a i n [ d b ] y 1 / c 1 t o y 4 / c 4 ? v o u t 1 , v o u t 2 t v , v 1 t o v 5 ? v o u t 1 , v o u t 2 y 1 t o y 4 ? y o u t 1 , y o u t 2 c 1 t o c 4 ? c o u t 1 , c o u t 2 1 k a u d i o s y s t e m f r e q u e n c y r e s p o n s e c h a r a c t e r i s t i c s 8 f r e q u e n c y [ h z ] 1 0 k 1 0 0 k 1 m 6 4 2 0 2 a u d i o s y s t e m i n p u t / o u t p u t g a i n [ d b ] l / r t v , l / r 1 t o l / r 5 ? l o u t 1 ( 0 d b ) l / r t v , l / r 1 t o l / r 5 ? l o u t 2 0 a u d i o s y s t e m d i s t o r t i o n v s . i n p u t a m p l i t u d e 0 . 0 0 2 i n p u t a m p l i t u d e [ v r m s ] 1 2 4 0 . 0 1 0 . 1 1 1 0 t o t a l h a r m o n i c d i s t o r t i o n [ % ] l o u t 1 o u t p u t ( 0 d b g a i n ) f = 1 k h z 4 0 0 h z h p f , 8 0 k h z l p f 3 l / r t v , l / r 1 t o l / r 5 ? l o u t 1 ( 6 d b ) l o u t 2 o u t p u t
? 20 CXA2079Q package outline unit: mm s o n y c o d e e i a j c o d e j e d e c c o d e 2 3 . 9 0 . 4 2 0 . 0 0 . 1 0 . 4 0 . 1 + 0 . 1 5 1 4 . 0 0 . 1 1 1 9 2 0 3 2 3 3 5 1 5 2 6 4 0 . 1 5 0 . 0 5 + 0 . 1 2 . 7 5 0 . 1 5 1 6 . 3 0 . 1 0 . 0 5 + 0 . 2 0 . 8 0 . 2 m 0 . 1 2 0 . 1 5 + 0 . 4 1 7 . 9 0 . 4 + 0 . 4 + 0 . 3 5 6 4 p i n q f p ( p l a s t i c ) q f p 6 4 p l 0 1 q f p 0 6 4 p 1 4 2 0 p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r / p a l l a d i u m 4 2 / c o p p e r a l l o y p a c k a g e s t r u c t u r e p l a t i n g 1 . 5 g 1 . 0

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